This invention relates to asynchronous differential communication.
Asynchronous communication, where a digital signal is sent from a transmitter and collected at a receiver, one direction at a time, requires that the start and stop of each message by unambiguously delimited. In most schemes, a certain number of extra bits are added to each message to accomplish this delimiting. These extra bits use available communication bandwidth.
A variety of signaling protocols are used in asynchronous communication. Referring to FIG. 1, Return to Zero (RZ) signaling indicates a logical 1 by raising the signal to an upper threshold voltage level, and then falling to a lower voltage level representing a 0 state, within one clock period. Successive logical ones (10) are each separated by these returns to zero. The No Return to Zero (NRZ) protocol signals a logical 1 by raising the signal to an upper threshold voltage at the falling edge of a clock period. No Return to Zero does not separate successive logical ones (12) with returns to zero. The No Return to Zero Inverse (NRZI) protocol signals a logical zero by a change of state at the rising edge of a clock period. A logical one is represented by not changing the state at the rising clock edge. Thus, successive logical ones (14) exhibit no change of state, while successive logical zeroes (16a, 16b) indicate a change of state at each clock period.
Each of the described protocols can be sent over the same hardware-level communication line. When sending digital messages at high speeds (for example, greater than 10.sup.6 bits per second) between relatively distant transmitters and receivers, differential signaling is preferred due to its greater noise immunity and tolerance of voltage offsets. Hardware differential signaling system 200 is illustrated in FIGS. 2A and 2B, where one wire 230a from transmitter 210 carries a V.sup.+ signal to receiver 220, and another wire 230b carries an inverse V.sup.- signal, and these two signals inversely mirror each other as in FIG. 2A. Since noise and voltage drifts tend to affect both differential wires 230a and 230b similarly, their relative signal voltages tend to remain synchronized, even if their absolute voltages tend to float. The relative voltages on the two signals V.sup.+ and V.sup.- define two distinct states for the differential wires: a J state, customarily defined as V.sup.+ higher than V.sup.-, and a K state, defined as V.sup.+ lower than V.sup.-. For Return to Zero and No Return to Zero signaling, the J state can be assigned as a logical one, and the K state can be assigned as a logical zero. For example, to implement No Return to Zero signaling, receiver 220 need only detect which of V.sup.+ and V.sup.- is higher than the other at each clock period.
As a further simplification, serial asynchronous bus transmission lines in computers often use No Return to Zero Inverse (NRZI) signaling using differential signaling hardware. Since NRZI assigns logical zero to a change in signal, and logical one to no change, NRZI differential signaling requires that receiver 220 only determine whether signal V.sup.+ has crossed signal V.sup.-, and not which signal wire is at a higher voltage than the other. In NRZI, any transition from state J to state K connotes a logical zero, while any persistence in either state J or state K connotes a logical one.
Data recovery of NRZI signals requires that the receiver use a clock running at a higher frequency than the data rate to oversample the state of the signal lines. Oversampling allows a certain number of data transitions to be sampled before the actual data is sent, so that the detector clock can be locked onto the periodicity of the incoming data. Once the receiver's clock is locked, the data transmission proceeds with data 0's being transmitted by a change in the state of the signal line(s) and data 1's being transmitted by leaving the signal lines unchanged. To maintain phase lock, the protocol must allow for some means of inserting transitions when the data comprises a long string of logical 1's, and thus would not otherwise have transitions. Inserting transitions is often termed "bit stuffing."
For any use of differential signaling, in any signaling protocol, some way of delimiting messages is needed. If formatting information is embedded within the data stream, the transmission medium's efficiency declines. However, if embedded formatting information is not used, the usual way to detect the end of a message is to detect that the transmitter has stopped sending. A long string of data 1's can provide this, but the string must be longer than any string of 1's that might occur during normal transmission.